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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2-Input Data Selector/Multiplexer High-Performance Silicon-Gate CMOS The MC54/74HC158 is identical in pinout to the LS158. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. These devices route 2 nibbles (A or B) to a single port (Y) as determined by the Select input. The data is presented at the outputs in inverted form for the HC158. A high level on the Output Enable input sets all four Y outputs to a high level for the HC158. MC54/74HC158 J SUFFIX CERAMIC PACKAGE CASE 620-10 1 16 16 1 N SUFFIX PLASTIC PACKAGE CASE 648-08 * * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Low Input Current: 1A High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 74 FETs or 18.5 Equivalent Gates LOGIC DIAGRAM A0 Nibble A Inputs A1 A2 A3 2 5 11 14 4 B0 Nibble B Inputs B1 B2 B3 3 6 10 13 7 9 12 Y0 Y1 Y2 Y3 Data Outputs ORDERING INFORMATION MC54HCXXXJ MC74HCXXXN MC74HCXXXD Ceramic Plastic SOIC 16 1 D SUFFIX SOIC PACKAGE CASE 751B-05 FUNCTION TABLE Inputs Output Enable H L L Select X L H Outputs Y0-Y3 H A0-A3 B0-B3 X = Don't Care A0-A3, B0-B3 = the levels of the respective Data-Word inputs. Pin 16 = VCC Pin 8 = GND Select Output Enable 1 15 Pinout: 16-Lead Plastic Package (Top View) Output VCC Enable 16 15 A3 14 B3 13 Y3 12 A2 11 B2 10 Y2 9 1 Select 2 A0 3 B0 4 Y0 5 A1 6 B1 7 Y1 8 GND 10/95 (c) Motorola, Inc. 1995 1 REV 7 IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII III IIIIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII MC54/74HC158 MAXIMUM RATINGS* Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 25 50 750 500 Vout Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA Iout DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature mW Tstg TL - 65 to + 150 260 300 _C _C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I III I I I I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII I I III I I III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter Min 2.0 0 Max 6.0 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout TA DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 2) VCC - 55 0 0 0 + 125 1000 500 400 _C ns tr, tf VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V DC CHARACTERISTICS (Voltages Referenced to GND) Symbol VIH Parameter Minimum High-Level Input Voltage Condition Vout = 0.1V or VCC -0.1V |Iout| 20A Vout = 0.1V or VCC - 0.1V |Iout| 20A Vin = VIH or VIL |Iout| 20A Vin =VIH or VIL |Iout| 4.0mA |Iout| 5.2mA VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 8 85C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 80 125C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.70 5.20 0.1 0.1 0.1 0.40 0.40 1.0 160 A A V Unit V VIL Maximum Low-Level Input Voltage V VOH Minimum High-Level Output Voltage V VOL Maximum Low-Level Output Voltage Vin = VIH or VIL |Iout| 20A Vin = VIH or VIL |Iout| 4.0mA |Iout| 5.2mA 4.5 6.0 6.0 6.0 Iin ICC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) Vin = VCC or GND Vin = VCC or GND Iout = 0A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC158 AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol tPLH, tPHL tPLH, tPHL tPLH, tPHL tTLH, tTHL Cin Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures 3 and 5) Maximum Propagation Delay, Select to Output Y (Figures 3 and 5) Maximum Propagation Delay, Output Enable to Output Y (Figures 4 and 5) Maximum Output Transition Time, Any Output (Figures 2 and 5) Maximum Input Capacitance VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 125 25 21 125 25 21 115 23 20 75 15 13 10 85C 155 31 26 155 31 26 145 29 25 95 19 16 10 125C 190 38 32 190 38 32 175 35 30 110 22 19 10 Unit ns ns ns ns pF NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Package)* 35 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). SWITCHING WAVEFORMS tr 90% Input Aor B tPHL 90% Output Y tTHL 50% 10% 50% 10% tf VCC tr 90% Select GND tPLH tPHL 90% Output Y tTLH tTHL 50% 10% 50% 10% tf VCC GND tPLH tTLH Figure 1. Figure 2. Y versus Select, Inverted tr Output Enable 90% 50% 10% tPLH 90% Output Y tTLH 50% 10% tf VCC OUTPUT DEVICE UNDER TEST TEST POINT GND tPHL CL* tTHL *Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HC158 PIN DESCRIPTIONS INPUTS A0-A3 (Pins 2,5,11,14) Nibble A inputs. The data present on these pins is transferred to the outputs when the Select input is at a low level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the HC158. B0-B3 (Pins 3,6,10,13) Nibble B inputs. The data present on these pins is transferred to the outputs when the Select input is at a high level and the Output Enable input is at a low level. The data is presented to the outputs in inverted form for the HC158. OUTPUTS Y0-Y3 (Pins 4,7,9,12) Data outputs. The selected input nibble is presented at these outputs when the Output Enable input is at a low level. The data present on these pins is in its inverted form for the HC158. For the Output Enable input at a high level, the outputs are at a high level for the HC158. CONTROL INPUTS Select (Pin 1) Nibble select. This input determines the data word to be transferred to the outputs. A low level on this input selects the A inputs and a high level selects the B inputs. Output Enable (Pin 15) Output Enable input. A low level on thisinput allows the selected data to be presented at the outputs. A high level on this input sets all of the outputs to a high level for the HC158. A0 2 4 B0 3 Y0 A1 5 7 B1 Nibble Inputs A2 6 Y1 11 9 Data Outputs B2 10 Y2 A3 14 12 B3 Output Enable Select 13 15 1 Y3 Figure 5. Expanded Logic Diagram MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HC158 OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620-10 ISSUE V -B1 8 -A16 9 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. DIM A B C D E F G J K L M N INCHES MIN MAX 0.750 0.785 0.240 0.295 -- 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 15 0 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 -- 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 15 0 1.01 0.51 -TSEATING PLANE N E F D G 16 PL K M J 16 PL 0.25 (0.010) M M T B S 0.25 (0.010) T A S -A16 9 N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R B 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.070 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0 10 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0 10 0.51 1.01 F S C L -TH G D 16 PL 0.25 (0.010) M SEATING PLANE K J TA M M -A- D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J 9 16 -B1 8 P 8 PL 0.25 (0.010) M B M G F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.25 0.10 0 7 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0 7 0.229 0.244 0.010 0.019 K C -TSEATING PLANE R X 45 M D 16 PL 0.25 (0.010) M J T B S A S High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HC158 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MOTOROLA CODELINE 6 *MC54/74HC158/D* MC54/74HC158/D High-Speed CMOS Logic Data DL129 -- Rev 6 |
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